LTC2451ITS8#TRPBF【PDF 4/20 页】IC ADC 16BIT DELTA SIG TSOT23-8

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LTC2451

2451fg

Discarding a Conversion Result and Initiating a New

Conversion with Optional Configuration Updating

At the conclusion of a conversion cycle, a write cycle

can be initiated. Once the write cycle is acknowledged, a

STOP (P) command initiates a new conversion. If a new

configuration is required, this data can be written into the

device and a STOP command initiates a new conversion

(see Figure 8).

Synchronizing the LTC2451 with the Global Address Call

The LTC2451 can also be synchronized with the global

address call (see Figure 9). To achieve this, the LTC2451

must first have completed the conversion cycle. The

master issues a START, followed by the LTC2451 global

address 1110111, and a write request. The LTC2451 will

be selected and acknowledge the request. If desired, the

master then sends the write byte to program the 30Hz

or 60Hz mode. After the optional write byte, the master

ends the write operation with a STOP. This will update

the configuration registers (if a write byte was sent) and

initiate a new conversion on the LTC2451, as shown in

Figure 9. In order to synchronize the start of the conver-

sion without affecting the configuration registers, the

write operation can be aborted with a STOP. This initiates

a new conversion on the LTC2451 without changing the

configuration registers.

PRESERVING THE CONVERTER ACCURACY

TheLTC2451isdesignedtodramaticallyreducetheconver-

sion result’s sensitivity to device decoupling, PCB layout,

antialiasing circuits, line and frequency perturbations.

Nevertheless, in order to preserve the high accuracy capa-

bility of this part, some simple precautions are desirable.

Digital Signal Levels

Due to the nature of CMOS logic, it is advisable to keep

input digital signals near GND or VCC. Voltages in the

range of 0.5V to VCC – 0.5V may result in additional cur-

rent leakage from the part.

Driving VCC and GND

In relation to the VCC and GND pins, the LTC2451 com-

bines internal high frequency decoupling with damping

elements, which reduce the ADC performance sensitivity

to PCB layout and external components. Nevertheless, the

very high accuracy of this converter is best preserved by

careful low and high frequency power supply decoupling.

A 0.1F, high quality, ceramic capacitor in parallel with a

10F ceramic capacitor should be connected between the

VCC and GND pins, as close as possible to the package.

The 0.1F capacitor should be placed closest to the ADC.

Figure 8. Start a New Conversion without Reading Old Conversion Result

APPLICATIONS INFORMATION

Figure 9. Synchronize the LTC2451 with the Global Address Call

SLEEP

7-BIT ADDRESS

(0010100)

WRITE

(OPTIONAL)

W ACK

DATA INPUT

CONVERSION

2451 F08

GLOBAL ADDRESS

(1110111)

SLEEP

CONVERSION

ACK

WRITE (OPTIONAL)

2451 F09

DATA INPUT

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